Learn about the workflow for generating readable and synthesisable HDL code from your MATLAB algorithms and Simulink models using HDL Coder.
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Do you want to prototype and test your algorithms on an FPGA while spending less time on HDL implementation?
Do you find it difficult to analyse, explore, and share HDL implementations of algorithms?
In this webinar, we demonstrate the workflow for generating readable and synthesisable HDL code from your MATLAB algorithms and Simulink models using HDL Coder. The generated HDL code can be used for FPGA or ASIC prototyping or production design.
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Vukosi Mboweni is a Junior Application Engineer at Opti-Num Solutions working in the Digital Engineering team. He attended the University of Pretoria where he obtained his Bachelors degree in Electrical Engineering and is currently completing his Masters degree in Electrical Engineering at the University of Cape Town. As an Application Engineer he supports companies with topics that include, but not limited to, wireless communication, C/C++ and HDL code generation, embedded systems and renewable energy.
